1. Field of the Invention
The present invention relates to a system for in-situ transistor level measurement of circuit timing information directly related to the switching events (logic transitions) of switching events of transistors of electrically active semiconductor integrated circuits.
2. Description of the Related Art
It is known in the prior art that various mechanisms in semiconductor devices can cause light emission. Detection of such light emission has been used to investigate semiconductor devices. For example, avalanche breakdown in insulators cause light emission, and detection of such light emission can point to the locations of failure in the device. Similar detection can be used to characterize electrostatic discharge in the device. In electrically stimulated (active) transistors accelerated carriers (electrons and holes), a.k.a. hot-carriers, emit light when the device draws current. Various emission microscopes have been used for detecting locations on the device where the electrical current drawn exceeds the expected levels and therefore could lead to locating failures in semiconductor devices. Some of these hot-carrier emission microscopes have been disclosed in the prior art. Examples of such emission microscopes are described in, for example, U.S. Pat. Nos. 4,680,635, 4,811,090, and 5,475,316.
For transistors (i.e. complementary meal oxide semiconductor (CMOS)) devices the current xe2x80x9cpulsexe2x80x9d coincides (in-time and characteristics) directly with the voltage transition responsible for the change in the state (logic) of the device. Of specific interest to this invention is resolving in time the hot-electron emissions from electrically active semiconductor transistor devices, to study the behavior and response of the device to electrical currents and the temporal relations of the current pulses with respect to each other. These temporal characteristics, along with the detection of the transition (pulse) itself is of critical importance in design and debug of integrated circuit (IC) devices. Previous and related works on the subject have been published and represented by the following papers:
All-Solid-State Microscope-Based System for Picosecond Time-Resolved Photoluminescence Measurements on II-VI semiconductors, G. S. Buller et al., Rev. Sci. Instrum. pp.2994, 63, (5), (1992);
Time-Resolved Photoluminescence Measurements in InGaAs/lnP Multiple-Quantum-Well Structures at 1.3-m Wavelengths by Use of Germanium Single-Photon Avalanche Photodiodes, G. S. Buller et al., Applied Optics, Vol 35 No. 6, (1996);
Analysis of Product Hot Electron Problems by Gated Emission Microscope, Khurana et al., IEEE/IRPS (1986);
Ultrafast Microchannel Plate Photomultiplier, H. Kume et al., Appl. Optics, Vol 27, No. 6, 15 (1988); and
Two-Dimensional Time-Resolved Imaging with 100-ps Resolution Using a Resistive Anode Photomultiplier Tube, S. Charboneau, et al., Rev. Sci. Instrum. 63 (11), (1992).
Notably, Khurana et al., demonstrated that photoluminescence hot-carrier emission coincides in time and characteristics with the current pulse and thereby the voltage switching of a transistor, thereby teaching that, in addition to failure analysis (location ofxe2x80x9chot-spotsxe2x80x9d where the device may be drawing current in excess of its design), the phenomenon can also be used for obtaining circuit timing information (switching) and therefore used for IC device debug and circuit design. See, also, U.S. Pat. No. 5,940,545 to Kash et al., disclosing a system for such an investigation.
As can be appreciated from the above-cited works, the light emission in semiconductor devices is very faint. Accordingly, various optical and detection schemes have been proposed to more efficiently collect the emission and reduce the noise, i.e., increase collection fidelity, bandwidth, and speed of the collection and detection system. For example, commercially available low-noise microchannel photomultipliers (MCPs) have been used to amplify the collected light by many orders of magnitude. Also, avalanche photodiodes (APDs) coupled with very fast optoelectric circuits (i.e. time-to-amplitude converter (TAC)) have been used to provide high temporal resolution of the faint emission phenomena.
From the collection optics perspective, in separate applications various attempts have been made to increase the focusing/imaging and collection of light from microscopic samples of the overall optical system. In particular, efforts have been made to increase the numerical aperture (NA=n*sin xcex8; n being the index of refraction of the medium and xcex8 being the half-cone angle of the focusing beam) of the microscope objective lens. It has been long known that increasing the numerical aperture (NA) can be achieved by increasing not only the cone-angle but also increase the index of refraction, n, to match to that of the sample, and avoid the air (n=1) and sample interface index mismatch. One historical method for increasing xe2x80x9cnxe2x80x9d is to fill the air gap between a properly aberration corrected objective lens and the sample with an index matching oil that matches the index of refraction of the object. Where proper matching fluids are not available to achieve the index matching, other methods can be used, such as the use of a solid immersion lens (matching the material of the sample) placed between the object and the objective lens. Of course, one may use both techniques, i.e., use immersion lens and index matching fluid. The use of the above techniques is disclosed in, for example, U.S. Pat. Nos. 3,524,694, 3,711,186, and 3,912,378. More modem discussions of immersion lenses can be found in U.S. Pat. Nos. 4,634,234, 5,004,307, 5,208,648, 5,282,088 and Solid Immersion Microscopy, S. M. Mansfield, G.L. Report No. 4949, Stanford University 1992. In the case of solid immersion lenses, prior art lenses are plano-convex (i.e., hemispheres). That is, the bottom surface, i.e., the surface facing the object, is flat, while the top surface, i.e., the surface facing the objective lens is convex.
Semiconductor devices of particular interest to the present invention are ones that are packaged in flipchip format. In flipchip packaged devices the direct attachment between the IC device and package carrier alleviates the use of wire bonding of the IC xe2x80x9cchipxe2x80x9d to the carrier. Additionally, the transistors are readily accessible through the substrate and therefore are not xe2x80x9cmaskedxe2x80x9d by the multiple layers of metal interconnect. Since the build, implementation and structure of flip chip packaged devices are well known; it will not be discussed here in details. Information relating to flip chip can be found in, for example, http://www.flipchip.com and http://world.std.com/xcx9chycomp/flippage.html.
Of specific interest is recent effort in the art to inspect such devices from the backside, i.e., from the substrate side, where the active layers of the IC transistors are readily accessible. One problem in probing flip chip packaged devices using conventional dynamic (timing) diagnostic methods, such as e-beam (voltage-contrast) probing, is that the critical nodes where timing information and fault isolation is critical are not readily accessible and masked by multiple levels of metal interconnects. Therefore, in order to expose the metal lines to the e-beam prober, one needs to either employ a forced ion beam (FIB) to xe2x80x9cdrillxe2x80x9d through the substrate and expose the critical node metallurgy, or pre-design opening for test and probe structures. The former is a time consuming and destructive method, and the latter wastes precious xe2x80x9creal-estatexe2x80x9d and in many cases does not represent the features of inertest to the circuit designer. Therefore, optical techniques have been employed to probe the device through the substrate (back-side). It must be noted that any IC could be repackaged for a flip/direct attach. Also, most advanced sub 0.18 micron and (below) devices that require intense rounds of timing measurements and debug are in flip chips package format, and thereby render themselves to back-side optical probing and detection. The reader is directed to these three articles, published in the Proceedings of 1998 International Test Conference (ITC ""98), October 18-22, 1998, Washington, D.C., IEEE Catalog No. RS00191:
Novel Optical Probing Technique for Flip Chip Packaged Microprocessors, Mario Paniccia, Travis Eiles, V. R. M. Rao and Wai Mun Yee.
Diagnosis and Characterization of Timing-Related Defects by Time-Dependent Light Emission, Dave Vallett, Leendert Huisman, and Phil Nigh.
Contactless Gigahertz Testing, W. Mertin, A. Leyk, U. Behnke, and V. Wittpahl.
Another article of interest is Picosecond Noninvasive Optical Detection of Internal Electrical Signals in Flip-Chip-Mounted Silicon Integrated Circuits, H. K. Heinrich, IBM J. Res. Develop. Vol 34, No. 2/3 1990.
Systems for imaging flip-chips from the backside through the silicon substrate are described in U.S. Pat. Nos. 5,208,648, 5,220,403 and 5,940,545.
However, in spite of the amount of work in the field, there is still no commercially viable system for device debug by time resolved measurements of hot electron emission. Amongst many issues facing the industry are:
Fast, reliable acquisition speed where the detected signal fidelity (i.e. bandwidth and resolution) is not compromised.
Ability to make measurements on low (or zero) capacitance devices (i.e. ones who employ silicon-on-insulator (SOI) in place of the regular silicon substrate)
High spatial resolution imaging and navigation to enable the location of node""s of interests in sub 0.2 micron devices
Cooling and power load management of the devices while under test (electrically stimulated), and operating without their heat-sink to allow for access to the device.
The present inventors provide a commercially viable integrated system for IC device debug by time resolved measurements of hot electron photo emission, providing high spatial resolution imaging and high temporal resolution detection. Moreover, the system enables cooling and temperature control of the device under test (DUT). Furthermore, the system enables navigation and imaging using the IC computer-aided design (CAD) layout. The inventive system is particularly useful for testing and debugging functional semiconductor integrated circuits having operational currents flowing therein.
In one aspect of the invention, an integrated system for testing an integrated circuit chip is provided. The chip under test is coupled to an Automated Test Equipment (ATE) that powers the device and stimulates it with programmed logic vectors and signals to simulate operating (functional and test) conditions of the chip. The inventive system comprises a controller receiving sync signals from the ATE; an optical imaging system for selectively imaging selected devices of the chip; a collection system for collecting photoemission from the chip and providing a time-resolved signal indicative of the photoemissions; an optomechanical navigation system for orienting the optical imaging system and the collection system with respect to the selected devices; and a thermal management system for cooling the chip to a temperature designated by the controller.
In another aspect of the invention, the inventive system comprises an x-y-z stage that is used to move the optics to the location of interest on the device under test, and focus and image the device(s) of interest. The navigation is performed in relation to a CAD layout of the IC. A mechanized shutter is used to variably define imaging areas within the field of view of the optics. During navigation and target acquisition, the device is illuminated and is imaged with an image intensifier, thereby providing high spatial resolution. When a device to be tested has been acquired, i.e., placed within the imaging area, the illumination source is turned off and the device is stimulated with test signals. During the stimulation period, hot electron photoemission is collected by the optics and is imaged onto a fiber optics.
To provide the temporal resolution, emission detection is synchronized with the test signals, i.e., the automated test equipment (ATE). Light collected by the fiber optics is detected by an avalanche photodiode (APD), which is coupled to an avalanche quenching circuit, a time-to-amplitude converter (TAC), and a multi-channel analyzer. Optionally, the APD is gated so that it assumes the detection condition only just before a light emission is expected according to the sync signal from the ATE. This provides reduction in noise and increases the life of the APD.
One advantageous feature of the inventive system is the active temperature control of the DUT. In debugging an IC, one issue of interest is the behavior of the various devices at various operating temperatures. Such study can point to performance and reliability issues caused by changes in the operating temperatures, and also provide device designers with highly temperature dependent crucial device junction operating conditions. The inventive system enables testing of the DUT at various controlled temperatures. Temperature control is provided separately to the chamber""s interior and the DUT, and integrated with the optical imaging/detection system. According to one embodiment, cooling of the DUT is done using a cooling block with cooling fluid circulated therein. According to another embodiment, the DUT is cooled using liquid micro-spray cooling technique.
According to a particular feature of the invention, an immersion lens is used to increase the light collection efficiency and imaging resolution. In one inventive embodiment, the index matched immersion lens is bi-convex and is pressured onto the DUT during emission detection to ensure direct (no air-gap) contact with the DUT.
An autofocus may also be provided for enhanced stability of the system. According to one embodiment, the autofocus is a passive system, i.e., includes no illumination source, but rather uses a feedback loop optimizing the collection rate of the photoemission light.